Can the PCIe Test Card be used to test PCI slots?
No. Although PCIe cards can be PCI legacy-compatible in terms of software, PCIe cards cannot be inserted into PCI slots as they have different pin configurations and the slots key differently. PCIe add-in cards are required to include an interference tab next to their PCIe edge connector to prevent mistaken insertion into PCI slots (see Figure 1 below).
Figure 1. Interference tab prevents insertion of PCIe cards into a PCI slot
What does a PCIe slot look like?
A PCIe slot looks similar to a PCI slot, however PCIe slots, compared to PCI slots, generally have a lower profile, a slightly different key spacing and are keyed on the opposite end. PCIe slots can range in length from x1 (1 lane) up to x32 (32 lanes). See Figure 2 for a side-by-side comparison of a x16 PCIe slot, a x1 PCIe slot and a PCI slot.
Figure 2. PCIe and PCI slots
What PCIe slot lengths can the PCIe Test Card be used in?
What generation of PCIe protocol can the PCIe Test Card be used in?
Which operating systems are these cards compatible with?
Do I need a device driver to use these cards?
Are the device drivers compatible with all versions of BurnInTest and PCIeTest?
Does the PassMark PCIe Test card appear in my Device Manager as a new PCIe Device?
What should I do if PCIe Test card doesn't appear in my Device Manager?
What is the meaning of the 24 LEDs on the device Top Side / Bottom Side
What is the acceptable range of the measured voltage rails?
The acceptable range of the various voltages measured by the PCIe Test Card are based on the ranges specified in the PCIe Electromechanical and ATX Power Supply Specifications.
|+3.3V PCIe or 3.3Vaux||3.003V||3.60V|
Why are there so many LEDs on the PCIe Test Card dedicated to indicating 12V and 3.3V power?
Each power-indicator LED corresponds to a power pin on the PCIe edge connector. Each PCIe connector and PCIe card therefore has five +12V, three +3.3V and one 3.3Vaux contacts/pins, respectively. (Multiple pins per power rail facilitate a higher current capacity (1.1A per pin) in order to meet PCIe power delivery requirements.) Dedicated power-pin LEDs help to indicate whether any pins in the connector are failing to make contact or not supplying additional current.
Figure 3. Power Supply Pins on PCIe Edge Connectors
What power rails are used in PCIe?
What is the 3.3Vaux rail for?
How can you tell if the measured voltages fall within the acceptable range?
Out-of-spec voltage measurements are indicated to the user in four different ways.
What do transients or spikes on the power rails look like?
Transients due to electrical noise generally appears as sharp peaks or dips deviating from a more or less constant measured voltage. See the below figure for an example of the PCIe Test Card in 'voltage mode' detecting noise on the system power supply's 5V line.
The 12V and 5V DC rails measured directly from the ATX power supply are more likely to exhibit high frequency noise as DC rails supplied to the motherboard and subsequently to the PCIe slot are generally decoupled from noise at an early stage.
Can I run multiple copies of PCIeTest at the same time?
Can I run multiple cards at the same time?
Does the Molex/SATA power always have to be connected?
Can I run PCIeTest at the same time as BurnInTest?
Is the PCIe Test Card hot-pluggable?
What type of PCIe data transfer type does the PCIe Test card use?
The red Error LED goes on. What does this mean?
What maximum speed should I expect from my PCIe slot?
PCIe Gen2.0 is normally quoted as 5Gbps per lane. Data rates will never reach these speeds on a real device because some signaling bandwidth is used by 8b/10b bit encoding, TLP, DLLP and PLP overhead. On a correctly functioning PC with a single PCIe device connected, you should typically see measured maximum speed results in the order of approximately:
*The PCIe Test Card has a maximum bandwidth of 1325 MBps, so the card cannot benchmark up to the PCIe Gen 2.0 maximum theoretical x4 bandwidth of ~1850 MBps.
Is there an Application Programming Interface available?
Is the firmware on the PCIe Test Card upgradeable?
Does PCIe Test card detect low-level errors in communication?
Yes, When running loopback test, PCIe Test application reports following low-level errors:
|Name of Error||Classification & severity||Layer Detected|
|Replay Number Rollover||Correctable||Link|
|Poisoned TLP Received||Uncorrectable - Non Fatal||Transaction|
|ECRC Check Failed||Uncorrectable - Non Fatal||Transaction|
|Unsupported Request||Uncorrectable - Non Fatal||Transaction|
|Completion Time-out||Uncorrectable - Non Fatal||Transaction|
|Completion Abort||Uncorrectable - Non Fatal||Transaction|
|Unexpected Completion||Uncorrectable - Non Fatal||Transaction|
|Training Error||Uncorrectable - Fatal||Physical|
|DLL Protocol Error||Uncorrectable - Fatal||Link|
|Receiver Overflow||Uncorrectable - Fatal||Transaction|
|Flow Control Protocol Error||Uncorrectable - Fatal||Transaction|
|Malformed TLP||Uncorrectable - Fatal||Transaction|
Based on severity, PCIe errors reported by application are categorized as below: