This is a post to document some investigation we did into the AMD Llano CPUs.
These are also known as AMD Fusion chips, or the 12h family. Chips in this series include the A6-3600, A6-3650, A8-3850, and about a dozen other models.
We have had several customers query us about benchmark results for this series of chips.
What was reported was that a number of these CPUs performed very badly on the Integer Maths test and the Prime number test.
Here is a graph showing the spread of the results across 180 difference PCs with the AMD-A6-3650 CPU. Results are in millions of operations per second.
About half of all systems show a 80% drop in performance on this integer maths test. The graph is similar for the prime number test, and also similar for the A8-3850 CPU. However the same behavior is not seen for other tests (like the floating point test).
So the bad behavior is only seen on the integer maths test and the prime number test.
The common thing about these two tests is that they make heavy use of integer division.
For several months we were unable to explain the behavior. We eliminated many possibilities such as over heating, bad configuration, etc.. but up until now couldn't come to any conclusion.
But a couple of days ago we came across this AMD document, "Revision Guide for AMD Family 12h Processors"
A section of this document describes, "Errata 665". These errata are lists of known bugs for a CPU.
Here is text for the Errata 665
This bug seems to closely match up with the behavior we are seeing. While we can't be 100% sure at this point we believe this bug maybe the cause of the poor benchmark results. These is a documented workaround, but in the BIOS we checked the motherboard manufacturers are not applying the correction.Code:665 Integer Divide Instruction May Cause Unpredictable Behavior Description Under a highly specific and detailed set of internal timing conditions, the processor core may abort a speculative DIV or IDIV integer divide instruction (due to the speculative execution being redirected, for example due to a mispredicted branch) but may hang or prematurely complete the first instruction of the non-speculative path. Potential Effect on System Unpredictable system behavior, usually resulting in a system hang. Suggested Workaround BIOS should set MSRC001_1029. This workaround alters the DIV/IDIV instruction latency specified in the Software Optimization Guide for AMD Family 10h and 12h Processors, order# 40546. With this workaround applied, the DIV/IDIV latency for AMD Family 12h Processors are similar to the DIV/IDIV latency for AMD Family 10h Processors. Fix Planned No
There also seems to be isolated incidents of this bug impacting real life applications as well, but on the whole there is very little information available about the impact.
Update: Same problem is seen for the AMD Athlon II X4 631, 641 & 651 CPUs and mobile CPUs like the A6-3400M. Which is to be expected as they also use the same 'Fusion' CPU core.